Constant voltage circuit

ABSTRACT

A current source generates a reference current. A first transistor is a depletion-type MOSFET arranged such that one terminal thereof is connected to the current source and its gate is connected to its source. A second transistor is an enhancement-type MOSFET arranged such that one terminal thereof is connected to the other terminal of the first transistor, the other terminal thereof is connected to a fixed voltage terminal, and its gate and drain are connected. A third MOSFET is an enhancement-type P-channel MOSFET arranged such that one terminal thereof is connected to the current source, the other terminal thereof is connected to the fixed voltage terminal, and its gate is connected to a connection node connecting the first and second transistors. A constant voltage circuit outputs at least a voltage that corresponds to the gate voltage of the third transistor or a voltage that corresponds to the gate voltage thereof.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitemploying a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

2. Description of the Related Art

In a semiconductor integrated circuit, a constant voltage circuit(reference voltage circuit) is employed in order to generate a constantvoltage that does not fluctuate with fluctuation in the power supplyvoltage or fluctuation in the temperature. Patent documents 1 and 2 eachdisclose a constant voltage circuit employing MOSFETs. FIG. 1 is acircuit diagram which shows a configuration of a constant voltagecircuit 200 according to a comparison technique. The constant voltagecircuit 200 includes a first transistor M11 and a second transistor M12sequentially stacked between the power supply terminal and the groundterminal. The first transistor M11 is configured as a depletion-typeN-channel MOSFET, and is arranged such that the gate thereof isconnected to the source thereof. The second transistor M12 is configuredas an enhancement-type N-channel MOSFET, and is arranged such that thegate thereof is connected to the drain thereof. A comparatively stablereference voltage Vref is generated at a connection node N1 thatconnects the first transistor M11 and the second transistor M12.

RELATED ART DOCUMENTS Patent Documents

[patent document 1]

-   Japanese Patent Application Laid Open No. H06-067744    [patent document 2]-   Japanese Patent Application Laid Open No. 2002-140124    [patent document 3]-   Japanese Patent Application Laid Open No. H07-092203

However, the constant voltage circuit 200 shown in FIG. 1 has a problemin that the reference voltage Vref fluctuates due to fluctuation in thepower supply voltage. In other words, such an arrangement has a problemof a low PSRR (power supply rejection ratio).

SUMMARY OF THE INVENTION

The present invention has been made in order to solve such a problem.Accordingly, it is a general purpose of an embodiment of the presentinvention to provide a constant voltage circuit having a high PSRR.

An embodiment of the present invention relates to a constant voltagecircuit. The constant voltage circuit comprises: a current sourceconfigured to generate a reference current; a depletion-type firstMOSFET (Metal Oxide Semiconductor Field Effect Transistor) arranged suchthat one terminal thereof is connected to the current source, and thegate thereof is connected to the source thereof; an enhancement-typesecond MOSFET arranged such that one terminal thereof is connected tothe other terminal of the first MOSFET, the other terminal thereof isconnected to a fixed voltage terminal, and the gate thereof is connectedto the drain thereof; and an enhancement-type P-channel third MOSFETarranged such that one terminal thereof is connected to the currentsource, the other terminal thereof is connected to the fixed voltageterminal, and the gate thereof is connected to a connection node thatconnects the first MOSFET and the second MOSFET. The constant voltagecircuit outputs at least one of a voltage that corresponds to the gatevoltage of the third MOSFET and a voltage that corresponds to the sourcevoltage of the third MOSFET.

Such an embodiment is capable of generating a stable reference voltageindependent of fluctuation in the power supply voltage.

Another embodiment of the present invention relates to a comparatorconfigured to make a comparison between a first voltage and a secondvoltage, and to generate an output voltage which represents thecomparison result. The comparator comprises: a differential pairconfigured to receive, as input signals, the first voltage and thesecond voltage; a tail current source configured to supply a tailcurrent to the differential pair; a load circuit connected to thedifferential pair; a source follower comprising a constant currentsource and an output transistor arranged on a path of the constantcurrent source, and configured such that the turn-on degree of theoutput transistor changes according to a current that flows through atransistor that is one component of the differential pair; and aconstant voltage element arranged between the transistor that is onecomponent of the differential pair and the control terminal of theoutput transistor.

With such an embodiment, the constant voltage element provides areduction in the extent of change in the gate voltage of the outputtransistor. Thus, such an arrangement provides an improved responsespeed.

Yet another embodiment of the present invention relates to a voltagemonitoring circuit configured to compare a voltage to be monitored witha predetermined reference voltage. The voltage monitoring circuitcomprises: the aforementioned constant voltage circuit configured togenerate the reference voltage; and the aforementioned comparatorconfigured to compare the voltage to be monitored with the referencevoltage.

It is to be noted that any arbitrary combination or rearrangement of theabove-described structural components and so forth is effective as andencompassed by the present embodiments.

Moreover, this summary of the invention does not necessarily describeall necessary features so that the invention may also be asub-combination of these described features.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, withreference to the accompanying drawings which are meant to be exemplary,not limiting, and wherein like elements are numbered alike in severalFigures, in which:

FIG. 1 is a circuit diagram which shows a configuration of a constantvoltage circuit according to a comparison technique;

FIGS. 2A and 2B are circuit diagrams each showing a configuration of aconstant voltage circuit according to a first embodiment;

FIGS. 3A through 3C are circuit diagrams each showing a modification ofthe constant voltage circuit;

FIG. 4 is a circuit diagram which shows a configuration of a comparatoraccording to a comparison technique;

FIG. 5 is a circuit diagram which shows a configuration of a comparatoraccording to a second embodiment;

FIG. 6 is a time chart which shows the operation of the comparator shownin FIG. 5; and

FIG. 7 is a circuit diagram which shows a configuration of a powersupply circuit including a constant voltage circuit and a comparator.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described based on preferred embodiments whichdo not intend to limit the scope of the present invention but exemplifythe invention. All of the features and the combinations thereofdescribed in the embodiment are not necessarily essential to theinvention.

In the present specification, the state represented by the phrase “themember A is connected to the member B” includes a state in which themember A is indirectly connected to the member B via another member thatdoes not substantially affect the electric connection therebetween, orthat does not damage the functions or effects of the connectiontherebetween, in addition to a state in which the member A is physicallyand directly connected to the member B. Similarly, the state representedby the phrase “the member C is provided between the member A and themember B” includes a state in which the member A is indirectly connectedto the member C, or the member B is indirectly connected to the member Cvia another member that does not substantially affect the electricconnection therebetween, or that does not damage the functions oreffects of the connection therebetween, in addition to a state in whichthe member A is directly connected to the member C, or the member B isdirectly connected to the member C.

First Embodiment

FIGS. 2A and 2B are circuit diagrams each showing a configuration of aconstant voltage circuit 100 according to a first embodiment. Theconstant voltage circuit 100 includes a current source 10, a firsttransistor M1, a second transistor M2, and a third transistor M3.

The current source 10 generates a reference current Iref. The onlydifference between FIG. 2A and FIG. 2B is in the configuration of thecurrent source 10. The configuration of the current source 10 will bedescribed later.

The first transistor M1 is configured as a depletion-type P-channelMOSFET (Metal Oxide Semiconductor Field Effect Transistor), and isarranged such that one terminal (source) thereof is connected to thecurrent source 10 and the gate thereof is connected to the sourcethereof.

The second transistor M2 is configured as an enhancement-type P-channelMOSFET, and is arranged such that one terminal (source) is connected tothe other terminal (drain) of the first transistor M1, and the otherterminal (drain) thereof is connected to a fixed voltage terminal(ground terminal). Furthermore, the second transistor M2 is arrangedsuch that the gate thereof is connected to the drain thereof.

The third transistor M3 is configured as an enhancement-type P-channelMOSFET, and is arranged such that one terminal (source) thereof isconnected to the current source 10, and the other terminal (drain)thereof is connected to the fixed voltage terminal (ground terminal).The gate of the third transistor M3 is connected to a connection node N1that connects the first transistor M1 and the second transistor M2.

The constant voltage circuit 100 outputs, as the reference voltage Vref,at least one of the voltages that occurs at a node N1 and a node N2.

(1) Voltage Vref1 that occurs at the gate of the third transistor M3(connection node that connects the first transistor M1 and the secondtransistor M2).

(2) Voltage Vref2 that occurs at the source N2 of the third transistorM3 (connection node that connects the first transistor M1 and thecurrent source 10).

The above is the basic configuration of the constant voltage circuit100.

Next, description will be made regarding the current source 10.

The current source 10 shown in FIG. 2A includes a fourth transistor M4,a seventh transistor M7, and a constant current source 12. The fourthtransistor M4 and the seventh transistor M7 are each configured as aP-channel MOSFET, and form a current mirror circuit. The fourthtransistor M4 duplicates the reference current Iref′ generated by theconstant current source 12, thereby generating the reference currentIref.

The current source 10 shown in FIG. 2B includes a fifth transistor M5and a sixth transistor M6. The fifth transistor M5 is configured as adepletion-type P-channel MOSFET, which is the same conduction type asthat of the first transistor M1. The sixth transistor M6 is configuredas a depletion-type P-channel MOSFET, which is the same conduction typeas that of the third transistor M3. The gates and the sources of thefifth transistor M5 and the sixth transistor M6 are each connected tothe power supply terminal (Vdd).

The drains of the fifth transistor M5 and the sixth transistor M6 areconnected together so as to form a common drain terminal, and thereference current Iref is output via this common drain terminal. A partof the reference current Iref, i.e., I_(M1), flows through the firsttransistor M1, and the remainder, i.e., I_(M3), flows through the thirdtransistor M3. The transistor size (gate width W/gate length L) of thefifth transistor M5 is adjusted by design so as to provide the flow ofthe current I_(M1). The transistor size of the sixth transistor M6 isadjusted by design so as to provide the flow of the current I_(M3).

The current source 10 shown in FIG. 2B has a simple configuration, andhas an advantage of requiring a small number of circuit elements. Itshould be noted that the configuration of the current source 10 is notrestricted to such arrangements shown in FIGS. 2A and 2B.

The above is the configuration of the constant voltage circuit 100.Next, description will be made regarding the operation thereof.

The current I_(M1), which is a part of the reference current Iref, flowsthrough a path including the first transistor M1 and the secondtransistor M2. As a result, the electric potential Vref1 at theconnection node N1 is stabilized to Vref=Vth_(M2) . . . (1).

Here, Vth_(M2) represents the gate-source threshold voltage of thesecond transistor M2.

Furthermore, the current I_(M3), which is a part of the referencecurrent Iref, flows through the third transistor M3. Thus, the electricpotential Vref2 at the connection node N2 is stabilized toVref2=Vref1+Vth_(M3)=Vth_(M2)+Vth_(M3) . . . (2). Here, Vth_(M3)represents the gate-source threshold voltage of the third transistor M3.

With the constant voltage circuits 100 shown in FIGS. 2A and 2B, bymaintaining the reference current Iref1 at a constant value, such anarrangement is capable of stably maintaining the reference voltagesVref1 and Vref2, respectively represented by Expressions (1) and (2).

The advantages of the constant voltage circuits 100 shown in FIGS. 2Aand 2B can be clearly understood in comparison with the constant voltagecircuit 200 shown in FIG. 1. With the constant voltage circuit 200 shownin FIG. 1, if the power supply voltage Vdd fluctuates, the drain voltageof the first transistor M11 also fluctuates. Accordingly, the operatingpoints of the first transistor M1 and the second transistor M2 eachfluctuate according to the fluctuation in the power supply voltage Vdd.As a result, the reference voltage Vref fluctuates due to the effects ofthe power supply voltage Vdd.

In contrast, with the constant voltage circuits 100 shown in FIGS. 2Aand 2B, the third transistor M3 functions as a clamping elementconfigured to stabilize the electric potential at the second node N2,i.e., the source voltage of the first transistor M1. Thus, even if thepower supply voltage Vdd fluctuates, the operating points of the firsttransistor M1 and the second transistor M2 do not fluctuate. Thus, suchan arrangement is capable of preventing the reference voltages Vref2 andVref1 from fluctuating. That is to say, the constant voltage circuit 100provides a higher PSRR than that of the constant voltage circuit 200shown in FIG. 1.

It should be noted that the transistor size of the third transistor M3is preferably designed to be greater than the sizes of the firsttransistor M1 and the second transistor M2. Due to the large transistorsize of the third transistor M3, the drain-source voltage VdsM3 of thethird transistor M3 becomes smaller. As a result, even in a state inwhich the power supply voltage Vdd is low, such an arrangement ensuresthat the source voltage of the first transistor M1 is a sufficientlyhigh voltage.

Conversely, in a case in which a sufficiently large voltage can beemployed as the power supply voltage Vdd, the transistor size of thethird transistor M3, i.e., the gate-source threshold voltage Vth_(M3) ofthe third transistor M3, should be designed giving consideration to thevalue of the desired reference voltage Vref2.

Furthermore, the constant voltage circuit 100 has a configuration inwhich all the transistors are configured as P-channel MOSFETs. With acircuit in which P-channel MOSFETs and N-channel MOSFETs are mixed,because of process irregularities, there are irregularities fromdifferences in the characteristics of the P-channel MOSFETs and theN-channel MOSFETs. This leads to a problem of irregularities in theoperating point of the circuit. In contrast, the constant voltagecircuits 100 shown in FIGS. 2A and 2B each have an advantage of a stableoperating point of the circuit that is resistant to processirregularities.

Furthermore, by configuring the pair composed of the fifth transistor M5and the first transistor M1 as the same conduction-type transistors, andby configuring the pair composed of the sixth transistor M6 and thethird transistor M3 as the same conduction-type transistors, such anarrangement provides further improvement to the stability of thereference voltages Vref1 and Vref2 with respect to the effects offluctuation in the power supply voltage and fluctuation in thetemperature.

FIGS. 3A through 3C are circuit diagrams each showing a modification ofthe constant voltage circuit 100. The constant voltage circuit 100 ashown in FIG. 3A has the same configuration as that of the constantvoltage circuit 100 shown in FIG. 2, except that the first transistor M1and the second transistor M2 are each configured as an N-channel MOSFET.

The constant voltage circuit 100 b shown in FIG. 3B has the sameconfiguration as that of the constant voltage circuit 100 shown in FIG.2, except that the second transistor M2 is configured as an N-channelMOSFET.

The constant voltage circuit 100 c shown in FIG. 3C has the sameconfiguration as that of the constant voltage circuits 100 shown inFIGS. 2A and 2B, except that the first transistor M1 is configured as anN-channel MOSFET.

The constant voltage circuits 100 a through 100 c shown in FIGS. 3Athrough 3C are each capable of generating the stable reference voltagesVref1 and Vref2 which are resistant to the effects of irregularities inthe power supply voltage Vdd and irregularities in the temperature, inthe same way as with the constant voltage circuits 100 shown in FIGS. 2Aand 2B. The constant voltage circuits 100 a through 100 c shown in FIGS.3A through 3C each have a configuration including a mixture of P-channelMOSFETs and N-channel MOSFETS. Accordingly, such arrangements areeffectively employed in a case in which a semiconductor process havingsmall process irregularities can be employed.

Second Embodiment

Next, description will be made regarding a comparator according to asecond embodiment.

In a semiconductor integrated circuit, a comparator is used in order tocompare the magnitudes of two voltages.

FIG. 4 is a circuit diagram which shows a configuration of a comparator400 according to a comparison technique. The comparator 400 includes adifferential amplifier 402 and a source follower 404. The differentialamplifier 402 includes a differential pair 406 (M21, M22), a currentmirror load 408 (M23, M24), and a tail current source 20.

The source follower 404 includes a constant current source 22 and anoutput transistor M25. The drain voltage of the transistor M22 is inputto the gate of the output transistor M25.

The comparator 400 shown in FIG. 4 has a problem in that the responsespeed is reduced due to the gate capacitance of the output transistorM25. That is to say, the gate voltage Vg of the output transistor M25 iscontrolled according to the magnitude relation between two inputvoltages INA and INB. In FIG. 4, the maximum value of the gate voltageVg is the difference between the power supply voltage Vdd and thedrain-source voltage Vds_(M24) of the transistor M24 (Vdd−Vds_(M24)).The minimum value of the gate voltage Vg is the sum of the voltage Vbiasthat occurs between both terminals of the tail current source 20 and thedrain-source voltage Vds_(M22) of the transistor M22, i.e.,(Vbias+Vds_(M22)).

Accordingly, with the comparator 400 shown in FIG. 4, there is a need tochange the gate voltage Vg of the output transistor M25 in a rangebetween (Vbias+Vds_(M22)) and (Vdd−Vds_(M24)). With a larger gatecapacitance of the output transistor M25, the period of time required toswitch the gate voltage Vg between (Vbias+Vds_(M22)) and (Vdd−Vds_(M24))becomes longer. This leads to poor responsiveness of the comparator 400.

A second embodiment is made in view of such a situation. Accordingly, itis an exemplary purpose thereof to provide a comparator having animproved response speed.

FIG. 5 is a circuit diagram which shows a configuration of a comparator300 according to the second embodiment. The comparator 300 is configuredto make a comparison between a first voltage INA and a second voltageINB, and to generate an output voltage OUT which represents thecomparison result.

The comparator 300 includes a differential amplifier 302 and a sourcefollower 304. The differential amplifier 302 includes a differentialpair 306 (M21, M22) respectively configured to receive the first voltageINA and the second voltage INB as input signals, a tail current source20 configured to supply a tail current to the differential pair 306, aload circuit 308 connected to the differential pair 306, and a constantvoltage element 24. The load circuit 308 is configured as a currentmirror circuit including transistors M23 and M24.

The source follower 304 includes a constant current source 22 and anoutput transistor M25 arranged on a path of the constant current source22. The gate of the output transistor M25 is connected to the drain ofthe transistor M24, which is one component of the load circuit 308. Theturn-on degree of the output transistor M25 changes according to thecurrent that flows through the transistor M22, which is one component ofthe differential pair 306.

As can be understood in comparison with the comparator 400 shown in FIG.4, the comparator 300 shown in FIG. 5 includes the constant voltageelement 24. The constant voltage element 24 is arranged between thedrain of the transistor M22, which is one component of the differentialpair 306, and the control terminal (gate) of the output transistorM25.ds

In FIG. 4, the constant voltage element 24 is configured as a P-channelMOSFET arranged such that the gate thereof is connected to the drainthereof. The voltage that occurs between both terminals of the constantvoltage element 24 is clamped to be equal to or greater than thegate-source threshold voltage of the MOSFET. As the constant voltageelement 24, a diode may be employed instead of such a P-channel MOSFET.Also, other kinds of constant voltage elements may be employed. Also,the constant voltage element 24 may include a MOSFET and a diodeconnected in series.

The above is the configuration of the comparator 300. Next, descriptionwill be made regarding the operation thereof. FIG. 6 is a time chartwhich shows the operation of the comparator 300 shown in FIG. 5. FIG. 6also shows the operation of the comparator 400 shown in FIG. 4, which isindicated by the lines of dashes and dots. The upper graph in the timechart shows the gate voltage Vg of the output transistor M25, and thelower graph shows the output voltage OUT.

In order to clarify the advantage of the comparator 300 according to theembodiment, first, description will be made regarding the operation ofthe comparator 400 indicated by the lines of dashes and dots shown inFIG. 4.

In the initial state (t<t0), the relation INA<INB is taken to hold true.In this state, current flows through the transistor M22 side, andaccordingly, the gate-source voltage Vgs of the output transistor M25 isset to its lower limit level VL′, which is approximately equal toVbias+Vds_(M22). The gate-source voltage Vgs of the output transistorM25 is greater than its threshold voltage Vthp. Accordingly, in thisstate, the output transistor M25 is on, and the output voltage OUT isset to high level (Vdd).

When INA becomes greater than INB at the time point t0, current flowsthrough the transistor M21 side, and accordingly, the current that flowsthrough the transistor M22 side is reduced. In this state, the gatevoltage Vg rises over time. When the gate-source voltage Vgs of theoutput transistor M25 becomes smaller than the threshold voltage Vthp atthe time point t2, the output transistor M25 is turned off, whereuponthe output voltage OUT transits to the low level (Vgnd).

That is to say, with the comparator 400 shown in FIG. 4, the level ofthe output voltage OUT transits after a delay time τ2 elapses after therelation between the input voltages INA and INB changes.

Next, description will be made regarding the operation of the comparator300 shown in FIG. 5 with reference to the solid lines.

In the initial state, the relation INA<INB is taken to hold true. Inthis state, current flows through the transistor M22 side, andaccordingly, the gate-source voltage Vgs of the output transistor M25 isset to its lower limit level VL, which is approximately equal toVbias+Vds_(M22)+Vth. That is to say, in the state in which INA<INB, thegate voltage Vg of the output transistor M25 is maintained at a levelthat is higher than that of the comparator 400 shown in FIG. 4 by thevoltage Vth that occurs between both terminals of the constant voltageelement 24.

When the relation between INA and INB changes to INA>INB at the timepoint t0, the gate voltage Vg of the output transistor M25 starts torise. After the delay time τ1 elapses, at the time point t1, thegate-source voltage Vgs of the output transistor M25 becomes smallerthan the threshold voltage Vthp, and accordingly, the output transistorM25 is turned off. As a result, the output voltage OUT transits fromhigh level to low level.

With the comparator 400 shown in FIG. 4, in order to switch thetransistor M25 from the off state to the on state, there is a need tochange the gate voltage Vg by an amount of change ΔVg′. In contrast,with the comparator 300 shown in FIG. 5, the amount of change ΔVg in thegate voltage Vg required to switch the transistor is smaller than thatrequired by the comparator 400 shown in FIG. 4. As a result, such anarrangement provides a reduction in the delay time before the outputvoltage OUT switches after the magnitude relation between the inputvoltages INA and INB changes. Thus, such an arrangement provides acomparator 300 having an improved response speed.

It should be noted that description has been made in the embodimentregarding an arrangement in which the differential pair 306 comprisesN-channel MOSFETs. Also, the present invention may be applied to acomparator including a differential pair 306 comprising P-channelMOSFETs.

Lastly, description will be made regarding a suitable application of theconstant voltage circuit 100 according to the first embodiment and thecomparator 300 according to the second embodiment.

FIG. 7 is a circuit diagram which shows a configuration of a powersupply circuit 500 including the constant voltage circuit 100 and thecomparator 300. The power supply circuit 500 includes a switchingregulator. The power supply circuit 500 includes a switching regulator502 and a overcurrent protection circuit (OCP) 504. The switchingregulator 502 includes a control unit 506, transistors M31 and M32, aninductor L1, and a capacitor C1. The switching regulator 502 has atypical configuration, and accordingly, description thereof will beomitted. The control unit 506 controls the duty ratio of the switchingoperation of the transistors M31 and M32 by means of pulse widthmodulation or pulse frequency modulation such that the output voltageVout is maintained at a constant level.

The overcurrent protection circuit 504 is configured as a voltagemonitoring circuit configured to compare a voltage V_(L1) thatcorresponds to a current I_(L1) that flows through the inductor L1 witha predetermined threshold voltage Vref, and to generate a signal OCPwhich indicates whether or not an overcurrent state occurs. When thesignal OCP indicates an overcurrent state, the control unit 506 stopsthe switching of the transistor M31 and M32. The overcurrent protectioncircuit 504 includes the constant voltage circuit 100 according to thefirst embodiment and the comparator 300 according to the secondembodiment.

With such a configuration, the constant voltage circuit 100 is capableof generating a stable reference voltage Vref. Thus, such an arrangementprovides accurate overcurrent protection. Furthermore, such anarrangement employs a comparator 300 having a high response speed,thereby providing a rapid overcurrent protection operation.

While the preferred embodiments of the present invention have beendescribed using specific terms, such description is for illustrativepurposes only, and it is to be understood that changes and variationsmay be made without departing from the spirit or scope of the appendedclaims.

1.-6. (canceled)
 7. A comparator configured to make a comparison betweena first voltage and a second voltage, and to generate an output voltagewhich represents the comparison result, the comparator comprising: adifferential pair configured to receive, as input signals, the firstvoltage and the second voltage; a tail current source configured tosupply a tail current to the differential pair; a load circuit connectedto the differential pair; a source follower comprising a current sourceand an output transistor arranged on a path of the current source, andconfigured such that the turn-on degree of the output transistor changesaccording to a current that flows through a transistor that is onecomponent of the differential pair; and a constant voltage elementarranged between the transistor that is one component of thedifferential pair and the control terminal of the output transistor. 8.A comparator according to claim 7, wherein the constant voltage elementcomprises a MOSFET arranged such that the gate thereof is connected tothe drain thereof.
 9. A comparator according to claim 7, wherein theconstant voltage element comprises a diode.
 10. (canceled)
 11. A voltagemonitoring circuit configured to compare a voltage to be monitored witha predetermined reference voltage, the voltage monitoring circuitcomprising: a constant voltage circuit configured to generate thereference voltage; and a comparator according to claim 7, configured tocompare the voltage to be monitored with the reference voltage.